The present invention relates to an SRAM (static random access memory) device in which memory cells can be arranged with a high density.
A CMOS type SRAM device having a 6-transistor configuration is known in the art. Such an SRAM device includes two unit circuits, each including a PMOS load transistor, an NMOS drive transistor and an NMOS access transistor. The PMOS load transistor and the NMOS drive transistor together form an inverter, and the NMOS access transistor connects the output of the inverter to a bit line. The two unit circuits are coupled together by connecting the input and the output of one inverter with those of the other inverter in a cross-coupled manner.
An SRAM device described in U.S. Pat. No. 5,744,844 (first conventional example) employs a lateral-type cell structure in which the PMOS load transistor of each unit is provided in an N-well region that is located in a central area of a memory cell region, the NMOS drive transistor and the NMOS access transistor of the first unit in a left-side P-well region, and the NMOS drive transistor and the NMOS access transistor of the second unit in a right-side P-well region. In this way, the access speed can be increased while the cell area can be reduced, as compared with a conventional longitudinal-type cell structure having an N-well region in the upper half of each memory cell region and a P-well region in the lower half thereof. Herein, the longitudinal direction is defined as the direction in which bit lines extend, and the lateral direction as the direction in which word lines extend. U.S. Pat. No. 5,930,163 discloses a similar technique.
An SRAM device described in U.S. Pat. No. 6,240,009 (second conventional example) is a 6-transistor SRAM memory cell intended for a single-ended read, differential write operation, in which the gate width of the NMOS drive transistor of one unit is set to be smaller than that of the other unit so as to reduce the cell area.
In a 6-transistor SRAM memory cell, the cell current that flows from a bit line to a source line is determined by the channel width of the NMOS drive transistor and the NMOS access transistor. A smaller cell current means a greater bit line amplification delay. However, in the first conventional example, the two unit circuits are symmetric in terms of the size of the constituent transistors, whereby in order to increase the cell current to reduce the bit line amplification delay so as to realize a faster operation, it is necessary to increase the size of all of the six transistors, which leads to a substantial increase in the cell area. In the second conventional technique, the NMOS access transistors of the two units have the same gate width, whereby the current driving power of the NMOS drive transistor having a large gate width cannot be fully made use of.